Physics-based and compact models for self-heating in high-speed bipolar integrated circuits
چکیده
Bipolar transistors are extremely sensitive to temperature variations. Moreover, the adoption of advanced isolation techniques such as silicon-on-insulator (SOI) and deeptrench isolation (DTI) to increase device speed also dramatically increases self-heating, due to the poor thermal conductivity of silicon dioxide. In many cases, an estimate of self-heating is needed before fabrication. However, analytical models for the thermal resistance of bipolar transistors exist only for a limited range of device geometries [1]–[3]. In this work we present numerical simulations and compact models of thermal resistance for bipolar transistors in a variety of geometries, including shallowand deep-trench isolation, and bulk and SOI substrates. The numerical simulation is validated on experimental data, and is used as a guide in developing new analytical compact models, which can then be used for both manual calculations and computer-aided design. No fitting parameters are necessary, and the total thermal resistance is obtained as a series or parallel composition of terms, each corresponding to a geometric feature.