Intel Discloses New IA-64 Features 3/8/99

In a series of talks at the recent Intel Developers Forum, the company tantalized industry watchers by dribbling out a few more details about its IA-64 instruction set and its first implementation, Merced. In a joint presentation by Intel’s John Crawford and Hewlett-Packard’s Jerry Huck, the two architects shed additional light on the IA-64 design. They provided further details on the architecture’s support for predication and speculation and also described IA-64’s branch architecture. A newly disclosed feature, rotating registers, provides an efficient way to unroll loops while minimizing code expansion. In other talks, Intel disclosed that Merced and its first chip set, the 460GX, will support high-availability features required in large servers. The company asserts that fourprocessor Merced servers will deliver more performance on the TPC-C benchmark than four-way servers using 1-GHz Alpha 21264 processors or 750-MHz UltraSparc-3 processors, two key Merced rivals that are expected to ship next year. But it has yet to disclose any details about clock speed, bus bandwidth, or other metrics to support this position.