Solving Boolean Satissability with Dynamic Hardware Conngurations

Boolean satissability (SAT) is a core computer science problem with many important commercial applications. An NP-complete problem, many diierent approaches for accelerating SAT either in hardware or software have been proposed. In particular, our prior work studied mechanisms for accelerating SAT using conngurable hardware to implement formula-speciic solver circuits. In spite of this progress, SAT solver runtimes still show room for further improvement. In this paper, we discuss further improvements to conngurable-hardware-based SAT solvers. We discuss how dynamic techniques can be used to add the new solver circuitry to the hardware during run-time. By examining the basic solver structure, we explore how it can be best designed to support such dynamic reconnguration techniques. These approaches lead to several hundred times speedups for many problems. Overall, this work ooers a concrete example of how aggressively employing on-they reconngurability can enable runtime learning processes in hardware. As such, this work opens new opportunities for high performance computing using dynamically reconngurable hardware.