An Efficient Implementation of Floating Point Multiplier using Verilog

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE754 standard based floating point representation. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed This project implements high speed implementation of a floating point arithmetic unit which can perform multiplication function on 32-bit operands. Multiplication is one of the common arithmetic operations; this floating point multiplication handles various conditions like overflow, underflow, normalization, rounding. In this project we use IEEE rounding method for perform the rounding of the resulted number. This project reviews the implementation of an IEEE 754 single precision floating point multiplier the multiplier implementation handles the overflow and underflow cases. Pre-normalization unit and post normalization units are also discussed along with exceptional handling. All the functions are built by feasible efficient algorithms with several changes incorporated that can improve overall latency, and if pipelined then higher throughput. The algorithms are modeled in Verilog HDL, the RTL code for multiplier is synthesized using Xilinx and the multiplier is simulated using