A 100-Gb/s Real-time Burst-mode Coherent PDM-DQPSK Receiver

We demonstrate a 100-Gb/s real-time coherent burst-mode receiver for the first time, based on 32-GSa/s low-profile ADCs. A particularly designed DSP architecture was implemented for rapid burst data recovery, FTL transience compensation and effective channel equalization. Introduction With the rapidly increasing bandwidth demand in recent years, the cost and power consumption for transceiving and switching data in optical networks tend to become tremendous and intolerable. All-optical burst networks have reattracted attention to tackle this challenge by eliminating the costly and power consuming O/E/O conversion and electrical switching at some switching nodes in metro and regional areas 1,2 . With the channel bit rate reaching 100 Gb/s or beyond, coherent technology is desirable to boost the capacity in an optical burst network with reasonably long reach. Recently, several studies on the coherent burst-mode receiver (BMR) have been reported 3-7 . One representative work realized 112-Gb/s polarization division multiplexing (differential) quadrature phase shift keying (PDM-(D)QPSK) burst-mode transceivers with fast wavelength tuning using offline digital signal processing (DSP) 3,4 . Another work demonstrated 28-Gb/s real-time PDM-QPSK burst-mode receiver 5,6 , in which special header design was employed for polarization demultiplexing, with no chromatic dispersion (CD) or polarization mode dispersion (PMD) compensation implemented. Previously, we have proposed a data-aided (DA) DSP architecture with complete function blocks to support fast and stable data recovery and to alleviate various impairments caused by fiber links, fast tunable lasers (FTLs), etc. 7 . In this paper, we implement a 100-Gb/s PDM-DQPSK coherent BMR with real-time DSP based on field-programmable gate arrays (FPGAs). Low-profile 32-GSa/s analog-to-digital convertors (ADCs) are employed, with the worst effective number of bits (ENOB) being only 2.5 bits. Improved DSP architecture is realized, which facilitates rapid burst data recovery despite of FTL transience induced impairments. Optical bursts reception after 500-km transmission is successfully demonstrated. The real-time 100-Gb/s BMR demonstration validated the technical feasibility of 100-Gb/s burst-mode transmission, implying the practicability of high-speed burst transceiving in optical burst metro networks. Real-time BMR Prototype Implementation The real-time coherent BMR prototype is composed of an optical frontend, four electrical signal interface modules and a DSP module, as shown in Fig. 1. One of the four interface modules acts as the master which synchronizes and controls the others. Each interface module consists of a low-pass filter (LPF), an ADC, and an FPGA of the 1 st type (FPGA1). The FPGA1 deserializes the high-speed data streams and carries out some pre-processing. Then the tributary electrical signals are fed into the DSP module, which consists of one or multiple FPGAs of the 2 nd type (FPGA2) optimized for the main processing. In our demonstration, four commercial 32GSa/s ADCs were employed. With respect to the 100-Gb/s, 25-GBaud PDM-DQPSK optical signal, the 32-GSa/s ADCs support at most a 1.28-Sa/sym sampling ratio, which will inevitably cause some degradation in the BMR performance. Furthermore, the four ADC cores interleaved in each ADC were observed to behave differently, resulting in severe 2.0 2.5 3.0 3.5 4.0 4.5 5.0 300 3000 30000 E N O B ( b it s) Frequency (MHz) Master Slave1 Slave2 Slave3 Fig. 2: ENOB of the ADCs versus analog bandwidth ADC FPGA1 Interface Module-Master ADC control ADC FPGA1 Interface Module-Slave 1 ADC control ADC FPGA1 Interface Module-Slave 2 ADC control ADC FPGA1 Interface Module-Slave 3 ADC control Clock