Design of a Very Low-power, Low-cost 60 GHz Receiver Front-End Implemented in 65 nm CMOS Technology

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale CMOS technologies is going on for some time now. While a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front–end achieves a record power consumption of only 43mW including lownoise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer and a baseband buffer (without this latter buffer the power consumption is even lower, only 29mW). Its pad-limited size is 0.55×1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30dB, the RF and IF bandwidths are 56.5-61.5 GHz and 0-1.5 GHz, respectively, its simulated minimum noise figure is 8.4 dB and its measured IP-1dB is -36 dBm.