Classification of Compiler Optimizations for High Performance, Small Area and Low Power in FPGAs
نویسندگان
چکیده
We propose a classification of high and low-level compiler optimizations to reduce the clock period, power consumption and area requirements in Field-programmable Gate Array (FPGA) architectures. The potential of each optimization, its effect on clock period, power and area and machine dependency is explained in detail.
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تاریخ انتشار 2003