Using RMII Master Mode

National Semiconductor’s PHYTER® family of products incorporate the Reduced Media Independent Interface (RMII) as described in the RMII revision 1.2 specification from the RMII Consortium. This interface may be used to connect a PHY device to a MAC in 10/100 Mb/s systems using a reduced number of pins relative to standard MII. In this mode, data is transferred two bits at a time using a 50 MHz reference clock for both transmit and receive MAC interfaces. The main advantage of RMII over standard MII is the reduced number of interface signals. This can improve PCB routing, and allows a PHY ASIC to be designed in a smaller package. A disadvantage to standard RMII is the requirement for an Elasticity Buffer in the receiver. This requirement is due to the fact that the Receive Data interface signals in RMII are synchronous to the local reference clock instead of the recovered Receive Clock present in standard MII. The Elasticity Buffer serves as a FIFO between the recovered clock and the RMII reference clock and is used to prevent loss of data due to slight frequency mismatches between the two clocks. The presence of the Elasticity Buffer introduces an uncertainty in the latency of the PHY receive datapath; this may be undesirable for systems requiring a high degree of determinism in the overall latency. As shown in Figure 1, the maximum supported packet size is a linear function of the nominal FIFO latency (bit depth).