Adaptive Computing and Run-time Reconfiguration

Adaptive Computing is a relatively new research area [1]. The main thrust of this research area so far has been on programmable/configurable hardware. Significant successes have been reported. The programmable gate array (FPGA) technology has matured producing very high-density gate arrays (~1 million gates) with lower configuration times. A variety of hardware platforms comprising of microprocessors and FPGA’s have been developed. A host of applications have been ported over to these platforms demonstrating significant speedup over the conventional microprocessor based implementation [2].