Design and Analysis of Power and Variability Aware Digital Summing Circuit

Due to aggressive scaling and process imperfection in sub-45 nm technology node Vt (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular 1-bit digital summing circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. The investigation is carried with ±3ó process parameters and ±10% VDD (supply voltage) variation by applying Gaussian distribution and Monte Carlo analysis at 22 nm technology node on HSPICE environment. Design guidelines are derived to select the most suitable topology for the design features required. Transmission Gate (TG)-based digital summing circuit is found to be the most robust against PVT variations. Hence, a TG-based digital summing circuit is implemented using carbon nanotube field effect transistor (CNFET). This implementation offers tighter spread in propagation delay (3×), power dissipation (1.14×) and EDP (energy delay product) (1.1×) at nominal voltage of VDD = 0.95V compared to MOSFET-based (TG – topology) digital summing circuit implying its robustness against PVT variations.