Forwardflow: Scalable, RAM-Based Dataflow Execution

Power (and thermal) limits have forced an industry-wide shift from increasingly complex uniprocessors to multicore chips with 4, 8, and even 16 simpler processor cores. Yet Amdahl’s Law suggests that these cores should not be too simple, lest they exacerbate even a parallel application’s sequential bottlenecks. Furthermore, running all cores at full speed will soon exceed the chip’s power envelope. Ideally, future CMPs should use cores that trade-off power and performance, allowing the system to scale up a core’s instruction-level parallelism (ILP) and memory-level parallelism (MLP) to improve sequential performance. This work presents the Forwardflow microarchitecture, which executes instructions out-of-order using RAM-based structures in lieu of non-scalable CAMor matrix-based mechanisms. Forwardflow dynamically builds an explicit internal dataflow representation from a conventional ISA, using forward dependence pointers to guide instruction wakeup, selection, and issue. Because all of Forwardflow’s major data structures are RAM-based, the instruction window scales large enough to tolerate long memory access times.