Automatic Generation of Executable Models from Structured Approach Real-Time Specifications

In this paper we present an automatic translation of real-time system specifications captured with Structured Analysis with Real-Time extension (SART) into SystemC executable models. SART is proposed as a front-end language for rapid SystemC model development. A synthesizable model of real-time system is thus obtained allowing for real-time performance estimation and behavior debugging at task-level. By means of the SystemC simulation kernel, both an early executions and timing specification validation are envisaged. Consequently, timing extension into SART is presented. After adding the model core functionality based on SART process specification (PSpec) and refining the HW/SW parts, a complete and synthesizable SystemC model is generated. Then, the advantages of SystemC executable models can be exploited to improve the real-time specification correctness, while the system designers stick to the engineering method of SART. Our solution thus enables the use of SART method in SoC and embedded system codesign, where SystemC simulation is increasingly used. A further benefit of the proposed approach is an integration of SystemC into the HW/SW development life-cycle of system and software engineering. A small example of a digital stop watch is presented demonstrating the benefits of this approach.