Programmable IP core for motion estimation: comparison of FPGA and ASIC based implementations

Design and Implementation of Parallel and Pipelined Distributive Arithmetic Based Discrete Wavelet Transform IP Core

The Discrete Wavelet Transform (DWT) has gained the reputation of being a very effective signal analysis tool for many practical applications. This paper presents an approach towards VLSI implementation of the Discrete Wavelet Transform for image compression. The design conforms to JPEG2000 standard and can be used for both lossy and lossless compression. In Discrete Wavelet transform, the filt...

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs

Design of High Throughput DCT Core Design by Efficient Computation Mechanism

This paper presents an approach towards VLSI implementation of the Discrete cosine Transform for image compression. Modules required for the corresponding ciruitThe design follows the JPEG standard and can be used for both lossy and lossless compression. In Discrete cosine transform, the filter implementation plays the key role. The poly phase structure is proposed for the filter implementation...

High Performance Single-Chip FPGA Rijndael Algorithm Implementations

This paper describes high performance single-chip FPGA implementations of the new Advanced Encryption Standard (AES) algorithm, Rijndael. The designs are implemented on the Virtex-E FPGA family of devices. FPGAs have proven to be very effective in implementing encryption algorithms. They provide more flexibility than ASIC implementations and produce higher data-rates than equivalent software im...

Exploring Many-Core Design Templates for FPGAs and ASICs

We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits o...