A Sub 100 mW H.264 [email protected] Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

نویسندگان

  • Yuichiro Murachi
  • Junichi Miyakoshi
  • Masaki Hamamoto
  • Takahiro Iinuma
  • Tomokazu Ishihara
  • Fang Yin
  • Jangchung Lee
  • Hiroshi Kawaguchi
  • Masahiko Yoshimoto
چکیده

PAPER Special Section on Advanced Technologies in Digital LSIs and Memories A Sub 100 mW H.264 [email protected] Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer Yuichiro MURACHI†a), Junichi MIYAKOSHI†, Members, Masaki HAMAMOTO†, Takahiro IINUMA†, Tomokazu ISHIHARA†, Fang YIN†, Jangchung LEE†, Hiroshi KAWAGUCHI†, Nonmembers, and Masahiko YOSHIMOTO†, Member

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSIoriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three r...

متن کامل

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allow...

متن کامل

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

For super-parallel video processing, we proposed a powerand area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirallyconnected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conv...

متن کامل

ASIP Solution for Implementation of H.264 Multi Resolution Motion Estimation

Motion estimation is the most important module in H.264 video encoding algorithm since it offer the best compression ratio compared to intra prediction and entropy encoding. However, using the allowed features for inter prediction such as variable block size matching, multi-reference frames and fractional pel search needs a lot of computation cycles. For this purpose, we propose in this paper a...

متن کامل

Reconfigurable Motion Estimation with Adaptive Search Range

In this paper, we propose an approach for motion-aware reconfigurable architecture to perform H.264/AVC Variable Block Size Motion Estimation (VBSME) algorithm. We show that by adaptively adjusting the search range on the reconfigurable hardware platform, the computational cost of motion estimation required for interframe encoding with H.264/AVC video compression standard can be reduced signifi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • IEICE Transactions

دوره 91-C  شماره 

صفحات  -

تاریخ انتشار 2008