High Speed and Area Efficient Fpga Implementation of Fir Filter Using Distributed Arithmetic

In this paper, high speed and area efficient multiplier-less architecture for Finite impulse response filter (FIR) based on distributed arithmetic is presented. The proposed Lookup table less architecture for FIR filter uses the speed advantage of Carry save adder. A modification in the shift accumulator stage yields both high speed and area savings. Furthermore, Memory reduction is possible since there is no Lookup table of precomputed values and only based on the input value the needed coefficient values are calculated. The proposed LUT less architecture was implemented on a Xilinx FPGA device. Number of slices, minimum period and maximum frequency were the performance metrics obtained for different filter orders and the results prove that the proposed method yields higher speed and smaller area when compared with the existing LUT-less architectures.