Interface Design Techniques for Single-Chip Systems

This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module interfaces. We show how the equation and interface considerations lead to more efficient queue structures for request buffering. For a specific single-chip design, we use simulation to show that: 1) For low request rates, queue structure is relatively unimportant to either system request bandwidth or service latency; 2) For a narrow range of request rates, queue structure has a significant impact on system latency but not bandwidth; 3) For high request rates, queue structure impacts bandwidth significantly; 4) As request service latencies increase relative to the queue size, the impact of the queue structure decreases; 5) Given a particular range of request rates, the complexity of particular queue structures can be traded off with the desired system bandwidth and latency performance. For a particular single-chip system, a maximum 29% bandwidth improvement and 60% latency improvement are achieved when using the more efficient