Generating Efficient Layouts from Optimized MOS Circuit Schematics RLE Technical Report

A technique has been developed for efficiently mapping arbitrary MOS circuit schematics into corresponding layouts. Since transistor sizings are preserved during this transformation to layout, this synthesis methodology can effectively be applied to optimized circuit schematics which typically include such sized transistors. The technique is based on a restructuring of the circuit description hierarchy into a new hierarchy based on topological rather than functional constraints. The method of restructuring was selected so as to ease the mapping of the leaf subcircuits into layout as well as to ensure that a majority of the possible local layout optimizations (such as connection by abutment) could be effected at the leaf subcircuit level. This allows the subsequent placement and routing of the generated leaf sublayouts to be done using conventional placement and routing techniques without a substantial area or performance penalty over a true full custom design. A program has been developed to implement this technique. Preliminary experiments in which the program has been applied to a number of module-size circuits have indicated that the layouts generated using this methodology are often superior in area and performance to those generated using more conventional automated layout techniques. Thesis Supervisor: Jonathan Allen Title: Professor of Electrical Engineering and Computer Science