The Spatial Characteristics of Load Instructions

Relatively little background work has been done to examine the miss behavior of all static and dynamic load instructions, especially in the context of the entire program. This study addresses this gap in knowledge by presenting the whole-program (as opposed to sampling) profiling results for load behavior. Specifically, this study confirms the conclusion of previous work in that a very small percentage of static loads (i.e. PCs) account for a disproportionately large percentage of the total L1 cache misses. This study also shows that an equally small percentage of unique effective addresses (EAs) account for a comparable percentage of the total L1 misses. In other words, a few "hot" PCs and EAs are responsible for a large percentage of the total L1 misses. Furthermore, a surprisingly large percentage of the dynamic loads can bypass the memory hierarchy by using store forwarding. However, the main contribution of this work is to quantify the whole-program behavior of static and dynamic loads with several different metrics that either confirm or contradict conventional thought or previous work.