Modified majority logic decoding of cyclic codes in hybrid-ARQ systems

Reliability information provided by sets of orthogonal check sums in a majority logic decoder for block codes is used in a type-I hybrid ARQ error control scheme. The reliability information is obtained through a simple modification of the majority logic decoding rule. It is shown that the reliability performance of Reed-Muller and other majority logic decodable codes can be substantially improved at the expense of a very small reduction in throughput. The simplicity of the decoding circuit enables implementation in systems with very high data rates.