Efficient Self-Reconfigurable Implementations Using On-chip Memory

The limited I/O bandwidth in reconfigurable devices results in a prohibitively high reconfiguration overhead for dynamically reconfigured FPGA-based platforms. Thus, the full potential of dynamic reconfiguration can not be exploited. Usually, any attainable speed-up by executing an application on hardware is diminished by the reconfiguration overhead. The self-reconfiguration concept aims at drastically reducing the reconfiguration overhead by performing dynamic reconfiguration on-chip without the intervention of an external host. Thus, using self-reconfiguration, a configurable device can alter its functionality autonomously. Implementations based on self-reconfiguration promise significant speed-up compared with conventional approaches [7, 8]. Self-reconfiguration was first introduced in [4, 5]. In [7, 8] self-reconfiguration was proposed to be realized by altering the configuration bit-stream, that is, on-chip logic accesses and alters the configuration bit-stream to reconfigure the device. Compared with conventional implementations, significant speed-up was achieved for string matching and genetic programming problems [7, 8]. However, the proposed approach in [7, 8] can be realized only using multi-context configurable devices that allow on-chip manipulation of the configuration bit-stream. In state-of-the-art FPGAs, direct manipulation of the configuration bit-stream can only be performed by an external host. Moreover, the complexity depends on the structure of the configuration bit-stream and the on-chip configuration mechanism, and has not been analyzed thus far.