Performance / Power Tradeo s in ASIC Multipliers
نویسنده
چکیده
This paper presents a wide array of e cient multipliers on an ASIC submicronic technology. Connection delays are taken into account through statistical wire lengthes. For power dissipation point of view, logic switching activity as well as glitching activity are both estimated. Firstly, the goal is to provide actual and accurate characterizations of classical multipliers. Secondly, most e cient architectures are compared such that optimized performance/power tradeo s are derived.
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تاریخ انتشار 2000