An All-Digital, High Data-Rate Parallel Receiver

The all-digital, high data-rate parallel receiver that is currently being developed jointly by the Jet Propulsion Laboratory (JPL) and Goddard Space Flight Center (GSFC) is presented. The role of JPL has been to analyze and simulate the receiver architecture and subsystems. Implementation of the receiver using fieldprogrammable gate arrays (FPGAs) and subsequent application-specific integrated circuit (ASIC) design take place at GSFC. The parallel receiver architecture that is currently being implemented differs from the original multirate filter-bank-based parallel architecture that was first developed by JPL. This alternate parallel receiver (APRX) is essentially a frequency-domain implementation of detection filtering and symbol-timing correction and is significantly easier to implement than the original version of the parallel receiver (PRX). It is shown that the APRX is equivalent to both the PRX and the conventional serial receiver in terms of performance. Results on the effect of analog antialiasing filter bandwidth and analog-to-digital sampling offset on the receiver performance are presented, along with discussion and results of the frequency-domain digital data-transition tracking-loop simulation.