Embedding and Verification of PSL using AsmL

In this paper, we propose a methodology to integrate the Property Specification Language (PSL) in the verification process of systems designed using Abstract States Machines (ASMs). We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL properties as part of the design. For the verification, we propose a technique based on the AsmL tool that translates the code containing both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage of the AsmL language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both a C# code and an FSM representation from an AsmL model. We applied our approach on SystemC designs, which are translated into AsmL models. Experimental results on a bus structure case study provided in the SystemC library showed a superiority of our approach to conventional verification.