The Cost of Uncore in Throughput-Oriented Many-Core Processors

Achieving performance through traditional techniques such as extracting more instruction level parallelism or increasing clock frequencies are losing their effectiveness due to the power wall. Multi-core processors have been put forth as a more power-performance efficient means of continuing performance scaling while coping with the realities of a power-limited design. Extrapolating the increase in the number of cores leads us to “many-core” systems, potentially containing hundreds of cores. The multi-/many-core approach is no panacea, however. As the number of cores increases, the overall system will need to provide more cache resources to feed all of these cores, and an everincreasingly complex interconnection network to tie all of these cores together. These additional “uncore” components are not free, and, unless carefully controlled, they may limit the effectiveness of many-core systems. We introduce a simple extension to Hill and Marty’s recent Amdahl’s Lawbased multi-core cost/performance model to account for the uncore components. From this model, we conclude that to sustain the scalability of future many-core systems, the uncore components must be designed to scale sub-linearly with respect to the overall core count.