Increasing Fault Simulation Performance Using Pre-synthesis Behavioral Model

-In this paper, a fault simulation method that utilizes behavioral pre-synthesis and gate level post-synthesis components models will be presented. In this method, an injected stuck at fault in a module will propagate through gates until it reaches the boundary of the module. Propagation of the fault in modules other than the one that it is initiated in will be done in behavioral models. This method is implemented in VHDL by implementing gate level and behavioral level fault propagation in VHDL. Using existing benchmarks, results show fault simulation speed improvement of a factor of 4 over gate-level fault simulation.