10-bit, 125 MS/s, 40 mW Pipelined ADC in 0.18 μm CMOS

This paper presents a 10-bit, 125 MS/s CMOS pipelined analog-to-digital converter (ADC). The power consumption of this ADC is just 40 mW at a supply voltage of 1.8 V, which is less than half that of other ADCs with an equivalent sampling rate. Low power consumption is achieved by using a flip-around digital-to-analog converter (FADAC) that reduces the power consumption of the front-end circuit by 50% compared to that of a conventional one. The ADC was fabricated using 0.18 μm CMOS technology, and the active area is 1.1 × 0.6 mm2. The measured peak signal-to-noise and distortion ratio (SNDR) is 54.2 dB with an 80 MHz input operating at a 125 MS/s sampling rate. The ADC will help reduce the power consumption of system-on-a-chips (SoCs) for digital consumer products and wireless communication equipment.