Transistor architecture: 45nm and beyond

1. Introduction The global need for high performance and low power computing continues to be a major driver of the semiconductor industry. In the high performance computing segment, complex projects (such as medical imaging, genomics research and weather prediction) need significant performance increases to fulfill growing expectations. The core computing segment requires performance increases due to expansion into usage models which exploit lifelike fully-integrated computing (such as language processing and immersive user experiences). The small computing segment is demanding more performance at lower power and cost, with the key drivers being anytime-anywhere context-aware personalized computing. For the past 40 years, relentless focus on Moore's Law transistor scaling has provided ever-increasing transistor performance and density. A decade ago, Moore's Law transistor scaling meant " classic " Dennard scaling [1] where oxide thickness (T ox), transistor length (L g) and transistor width (W) were scaled by a constant factor (1/k) in order to provide a delay improvement of 1/k at constant power density. However, " classic " Dennard scaling has become less influential after the 130nm node. In subsequent generations (90nm, 65nm, 45nm, 32nm, etc.) performance enhancers using new materials were added to continue to drive the transistor roadmap forward (e-SiGe, strained SiN for strain in the 90nm and 65nm nodes [2,3], and high-k metal-gate (HiK-MG) in the 45nm and 32nm nodes [4,5]). Modern CMOS scaling is increasingly a story of materials innovation. As we look beyond 32nm planar transistors, there are a number of challenges to be addressed (Fig. 1).