Verification of Parameterised FPGA Circuit Descriptions with Layout Information

Manual placement is commonly used in FPGA circuit design in order to achieve better resultsthan would be generated by automatic place and route algorithms. However, explicit place-ment of individual components in parameterised descriptions is tedious and error-prone. Inthis thesis we present a framework for the design and verification of parameterised hardwarelibraries with layout information. There are five main contributions: (1) We develop additions to the Quartz language and provide compiler support to allowthe addition of generic layout information to parameterised circuit descriptions describedusing iterative and recursive constructs. We show how functional combinators can be givenmultiple layout interpretations. (2) We provide a specification of layout correctness and develop a proof environment toallow the verification of parameterised Quartz circuit layouts. We prove a range of usefultheorems about common circuit layout expressions and achieve a high level of automation ofthe verification process. (3) We develop and verify a range of placed combinator libraries describing useful circuitstructures including rows, grids, trees and less regular examples. We show that our verifica-tion environment can not only establish correctness but also can highlight counter-exampleswhere layouts are incorrect. (4) We show how distributed specialisation can be used to achieve transparent HDL-levelspecialisation of circuits when some inputs are known. Distributed specialisation allows thecorrectness of specialised circuits to be proven more easily than using lower-level methods.We demonstrate the use of our layout framework to specialise parameterised circuits andshow that our system is able to achieve design compaction. (5) We describe and verify the layouts of five example circuits, including a butterfly network,binomial filter and matrix multiplier. We show that manual placement can reduce compilationtime, reduce logic area by up to 60%, reduce power consumption by up to 20% and increasemaximum clock frequency by up to 80% for unpipelined circuits and 48% for pipelinedcircuits.