A Configuration Memory Architecture for Fast Fpga Reconfiguration Unsw-cse-tr 0509

This report presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial reconfiguration that allows significant configuration re-use while switching from one circuit to another. This technique makes use of existing on-chip configuration fragments in order to construct later circuits thereby reducing the amount of configuration data that needs to be loaded onto the device. The proposed configuration memory works by reading on-chip configuration data into a buffer, modifying them based on the externally supplied data and writing them back to their original registers. A proptype implementation of the proposed design in a 90nm cell library suggested that the new memory added less than 1% area to a commercially available FPGA implemented using the same library. The proposed design reduced the reconfiguration time for a set of benchmark circuits by 63%. However, power consumption during reconfiguration increased by about 60% mainly becuase of an increased switching activity incured due to a read-modify-write strategy.