Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology

ABSTRACT This paper presents a design of a high speed Comparator design using 65nm digital CMOS technology on Cadence Virtuoso Design Tool. The proposed FLASH ADC Design consists of fully differential topology. The first stage provides a Voltage Divider circuit and the second stage is Comparator Design having high sampling frequency tolerance, and the high efficient common drain circuit provides high driving capability with relatively low power dissipation. It is used in more application for bandwidth and power and a high resolution is available for analog-to-digital converters (ADCs). Under 1 V supply voltage, the simulation results show that the proposed FLASH ADC Design is having a differential topology along with latching circuit.