From Verification to Implementation: UPPAAL to C++
نویسندگان
چکیده
Validation and Verification of safety critical systems is crucial and if done incorrectly can result in fatal loss. The research contribution is focused on providing the transformation mechanism from software verification to source code phase of software development life cycle. Modeling of the critical systems initializes with the formalism of requirements followed by early model verification. The verified model can be automated to get the high level language code via code generator. Basic steps of transformation starts with UPPAAL timed automaton as an input, then getting the XML structure of the automaton. On the basis of XML structure parse tree is generated to visualize the data structure to be used for the C++ source code generation. Finally the verification, kernel and elapsed time used by the safety, liveness, reachability, deadlock freeness properties and fairness property is presented. In real time systems, safety and deadlock freeness properties are among the most crucial verification properties because if the system is not safe then it leads to insecurities related to life, money, reputation and time. If the system is in deadlock state then the system is simply of no use. Thus verification of safety and deadlock freeness properties is mandatory as per the statistical report provided in the research.
منابع مشابه
Computer Science at Kent Verification of Timed Automata with Deadlines in Uppaal
Timed Automata with Deadlines (TAD) are a form of timed automata that admit a more naturalrepresentation of urgent actions, with the additional advantage of avoiding the most common form oftimelocks. We offer a compositional translation of a practically useful subset of TAD to timed safetyautomata (the well-known variant of timed automata where time progress conditions are expre...
متن کاملTowards the Analysis and Verification of EAST-ADL Models using UPPAAL PORT
A system’s architecture influence on the functions and other properties of embedded systems makes its highlevel analysis and verification very desirable. EAST-ADL is an architecture description language dedicated to automotive embedded system design with focus on structural and functional modeling. The behavioral description is not integrated within the execution semantics, which makes it harde...
متن کاملModel-checking and Model-based Testing of Automotive Embedded Systems Starting from the System Architecture
Nowadays, modern vehicles are equipped with electrical and electronic systems that implement highly complex functions such as anti-lock braking or cruise control. The use of such embedded systems in the automotive domain requires a development process that takes into account their complex features. In this context, architectural models have been introduced in system development as convenient ab...
متن کاملModelling And Verification Of Concurrent Programs Using UPPAAL
This paper describes the design and implementation of a library of reusable UPPAAL template processes which support reasoning and property checking of concurrent programs, e.g. to be realized in the Java programming language. The stimulus to the development of the library originated in the context of a systems programming undergraduate course. The library, though, can be of help to general prac...
متن کاملTools for Real-Time UML: Formal Verification and Code Synthesis
We present a real-time extension of UML statecharts to enable modelling and verification of real-timed constraints. For clarity, we shall consider a reasonable subset of the rich UML statechart model and extend it with real-time constructs (clocks, timed guards, invariants and real-time tasks). We have developed a a rule-based formal semantics for the obtained formalism, called hierarchical tim...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2016