A Multi-Layer Intermediate Representation for ASIP Design

The design of an application-specific instruction-set processor (ASIP) involves a number of basic steps, as shown in figure 1. The designer first specifies a set of applications that are characteristic for the target domain. This is done in a high-level language such as C. A compiler front-end then translates this application into an intermediate representation, which usually corresponds to some form of annotated graph structure, where the nodes represent instructions. This graph is then optimized and scheduled into time steps. At this point, candidate patterns for hardware implementation are extracted, and information about their frequency and benefit are stored with them. A subset of these patterns is selected, and the corresponding instruction set and processor description are generated. The last two steps can be iterated, feeding the new processor description back into the pattern finder. Figure 1: ASIP design methodology. Much of the quality of the outcome of this process depends on the intermediate representation (IR) employed. This representation needs to contain the complete information necessary for the design of an instruction set and the corresponding processor. Moreover the representation should provide easy access to the properties of the application that are most relevant to the design of an optimal solution of this kind. State-of-the-art intermediate representations for the design of ASIPs are targeted at the area of data-dominated applications, such as digital signal processors (DSPs), which consist of extensive computations compared to only relatively few control constructs. The IRs used in this domain therefore tend to concentrate on data dependencies, often together with some kind of frequency information indicating the relative likelihood of some block of instructions to be executed. In order to design a methodology for the control-dominated domain , however, a broader set of information in the intermediate representation is required. Applications in this area, of which network protocol header processing is a typical example, involve only small amounts of computation with a comparatively large number of control instructions such as branches. We are therefore also interested in the control flow of the application. But in order to 1 INTRODUCTION 4 improve our result, we would like to have as much further information about the application as possible, such as timing constraints and parallel scheduling possibilities. This data allows for solutions that are much better adapted to the actual environment that the processor will be used in. The Multi-Layer Intermediate Representation [1] is an example of an …