Memory Organization and Exploration for Embedded Systems-on-Silicon

The growing gap between processor and memory speeds makes memory issues a major bottleneck in the design of systems-on-silicon. When the system is designed for a targeted application (as is the case with embedded systems-onsilicon), several strategies can be employed to resolve this memory bandwidth bottleneck, including reorganization of data, exploiting locality of reference to tune the memory hierarchy, and intelligent partitioning of data amongst different levels of the memory hierarchy. From a system designer’s perspective, this requires an early memory exploration capability in order to evaluate its effects on system performance, cost and power, before the tasks of hardware and software co-design are performed. The research problems at this level require integration of the traditionally disjoint fields of computer architecture, compiler design, and digital CAD. This paper describes some strategies for memory organization and exploration that will aid system-level designers for future embedded systems-on-silicon.