Storage Mapping Optimization for Parallel Programs

Parallelization via Constrained Storage Mapping Optimization

A key problem for parallelizing compilers is to nd the good tradeo between memory expansion and parallelism. This paper is a new step towards solving this problem. A framework for parallel execution order and storage mapping computation is designed, allowing time and space optimization. Constrained expansion|a theoretical model for expansion strategies|is shown to be very useful in this context.

Optimization Flow for Algorithm Mapping on Graphics Cards

Graphics card architectures provide an optimal platform for parallel execution of many number crunching loop programs, ranging from fields like image processing to linear algebra. However, it is hard to efficiently map such algorithms to the graphics hardware, even with detailed insight into the architecture. This paper presents an optimization flow for mapping algorithms to the graphics hardwa...

Optimization of Storage Mappings for Parallel Programs

Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays

Methods for an efficient mapping of algorithms to parallel architectures are of utmost importance because many stateof-the-art embedded digital systems deploy parallelism to increase their computational power. This paper deals with the mapping of loop programs onto processor arrays implemented in an FPGA or available as (reconfigurable) coarsegrained processor architectures. Most existing work ...

Data Partitioning for a Good Node Performance

As a consequence of recent advances in interconnection network technology for MIMD parallel computers, optimizing communications in parallel programs has become a factor of secondary importance. For example, mapping processes onto processors is currently an issue of minor importance for some up-to-date distributed memory parallel computers, because the interconnection network guarantees a fairl...