A Fast Two-phase Micropipeline Control Wrapper for Standard Cell Implementation

A fast control wrapper for a micropipeline with two-phase control is presented. The wrapper is implemented in an Artisan 0.13µ commercial standard library that has not been augmented with any special cells for asynchronous design. The wrapper is approximately 25% faster than a more traditional approach that uses a Muller C-element. Introduction: Micropipelines [1] use control logic wrapped around compute blocks to implement asynchronous systems. Micropipelines have been used to implement significant designs, including complex microprocessors [2]. Four-phase control [3] means that the control lines between micropipeline stages undergo a low-to-high-to-low transition for each data movement between stages; while two-phase control implies either a single low-to-high or high-low transition. Typical micropipeline control logic use Muller C-elements which have efficient transistor level implementations for a small number of inputs (< 4). Large input C-elements can be implemented as trees of smaller C-elements or can be mapped directly to standard cells as described in [4]. Most micropipeline approaches use a bundled data signaling approach in which a single control wire is used for all data wires originating from a micropipeline stage. Delay elements are added to the control path to produce a matched control/datapath delay so that the latching signal from the control wrapper arrives at the output latches of the micropipeline stage at the same time as the data. In designs with thin pipeline stages, the performance of the control logic becomes an issue, with the control path becoming the performance limiter instead of the Submitted to Electronics Letters datapath. Control logic performance is also important if a micropipeline stage has finished a computation, and is waiting on an acknowledgment from a successor stage in order to latch the new computation, thus providing the new value to the successor stage. Acknowledgements propagate backwards through the pipeline, and thus do not have delay elements in their path. A Fast Two-Phase Wrapper: Figure 1 shows the two-phase micropipeline control wrapper used in the design of a five-stage pipelined MIPS-compatible processor [5]. Each bundled data input i consists of a group of data lines data_bundl_i and its associated control line Cin_i. Each predecessor stage (fanin) provides a data bundle, and each successor stage (fanout) provides an acknowledgement signal. The control is two-phase, so each Cin input and acknowledgement