’ Introduction : Advances in 3 - D Integrated Circuits , Systems , and CAD

h THREE-DIMENSIONAL INTEGRATION, a breakthrough technology to achieve “More Moore and More Than Moore,” provides numerous benefits such as better performance, lower power consumption, smaller form factor, and wider bandwidth than traditional 2-D integration technology. Three-dimensional stacking of heterogeneous silicon layers also enables heterogeneous 3-D integration. Thanks to the enormous efforts put into 3-D integration in academia and industry, a few 3-D products such as 3-D field-programmable gate array (FPGA) and through-silicon-via (TSV)-based dynamic random access memory (DRAM) have finally been commercialized in the semiconductor market. Commercialization of more diverse 3-D integrated circuit (IC) products, however, still requires novel solutions for various challenging issues such as effective heat removal and lack of standards, applications, and computer-aided design (CAD) tools for design, analysis, and optimization of 3-D ICs. The Special Issue on Advances in 3-D Integrated Circuits, Systems, and CAD Tools, published in IEEE Design & Test in July/August 2015 introduced seven papers to highlight recent research on 3-D integration. The papers covered a wide range of topics on 3-D ICs from 3-D IC manufacturing process and 3-D integration technology to thermal analysis, 3-D design-for-test architectures, 3-D integration of memory and logic, test methodologies for 3-D ICs, and 3-D memory architectures. As a second part of the Special Issue on Advances in 3-D Integrated Circuits, Systems, and CAD Tools, this special issue presents four more papers that highlight recent advances in test methodologies for 3-D interconnects, modeling of TSVs and TSV channels, memory architecture optimization for 3-D stacked DRAM, and codesign of 3-D CPUs and microfluidic pin-fin cooling structures. “Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects” by Huang et al., proposes a test methodology to detect delay faults in multipin interconnects in 3-D ICs with 10-ps resolution. The idea is to insert a multiplexer for each pitcher cell driving a 3-D interconnect and a multiplexer for each receiver cell so that a global ring structure is formed to test each 3-D interconnect. The authors also present a clock period measurement circuit to achieve a measurement accuracy of 10 ps. “High-Frequency Temperature-Dependent ThroughSilicon-Via (TSV) Model and High-Speed Channel Performance for 3-D ICs” by Lee et al., presents high-frequency temperature-dependent RLGC models for TSVs and TSV channels. The authors verify the models against measurement data and show the impact of temperature variation on noise coupling between two neighboring TSVs and between two neighboring TSV channels. Digital Object Identifier 10.1109/MDAT.2016.2519718