High Defect Coverage with Low-Power Test Sequences in a BIST Environment
چکیده
and difficult aspects of the circuit design cycle, driving the need for innovative solutions. To this end, researchers have proposed built-in self-test (BIST) as a powerful DFT technique for addressing highly complex VLSI testing problems. BIST designs include on-chip circuitry to provide test patterns and analyze output responses. Performing tests on the chip greatly reduces the need for complex external equipment. The most commonly used fault model for BIST of digital systems is the classical single stuck-at fault model. However, in the new CMOS nanometer technologies, defects do not always behave as stuck-at faults do.1 Therefore, test generation based on the stuck-at model alone is no longer sufficient for obtaining high defect coverage.2 A straightforward solution covering many misbehaviors that can occur in digital circuits would be to use multiple test generation techniques, each targeting a specific fault type (such as stuck-at, delay, or bridging). However, this solution is costly and impractical from a BIST viewpoint. An alternative solution might be the use of a single on-chip test pattern generator providing “universal” test sequences—sequences that target both conventional (stuck-at) and unconventional (delay, bridging, and stuck-open) fault types. The problem with this solution is that test application consumes excessive power because switching activity is significantly higher during test than during system mode.3 A standard test pattern sequence produced by a linear feedback shift-register (LFSR) consists of random multiple-input change (RMIC) patterns with a switching-activity rate of 0.5 (that is, an equal likelihood of 0 and 1). In this article, we propose a new BIST test generation technique that reduces the switching activity of test patterns generated during BIST while increasing the defect coverage. The technique, called random single-input change (RSIC), generates test patterns capable of detecting many different faulty behaviors. Moreover, RSIC test sequences have a low rate of switching activity.