A Novel Architecture For An Energy Efficient And High Speed Sar Adc

This brief involves the design and implementation of an energy-efficient and high speed SAR ADC. The DAC would be designed to reduce the power consumption by applying a switching scheme. The architecture of SAR module provides improved speed of conversion. Power consumption is one of the main design constraints in today ICs. For systems that are powered by small non rechargeable batteries over the entire life time, such as medical implant devices low power consumption is important. In these systems SAR ADCs are key components to interface between analog world and digital domain. The design is implemented using Very Highspeed Integrated Circuit Hardware Description Language (VHDL). The operations of SAR ADC are simulated using the Modelsim tool and SAR ADC design is synthesized using Xilinx tool.