Towards Efficient Hardware for Spike-processing Neural Networks

We present the requirements for a neurocomputer for spike-processing neural networks. In a simulation study we investigated the performance of available hardware and showed, that there is still a need for a specific neurocomputer dedicated to the simulation of spike-processing networks. On the basis of our simulation study and an investigation of the features of spike-processing networks we analyses the requirements for the design of dedicated hardware. An efficient hardware architecture should contain an event-list module, a sender-oriented connection module and a number of fixed-point processing units.