Leveraging Infrastructure IP for SoC Yield

Embedded Memory Test & Repair: Infrastructure IP for SOC Yield

Today’s System-on-Chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test & repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip Infrastructure IP. To maximi...

Guest Editor's Introduction: What is Infrastructure IP?

0740-7475/02/$17.00 © 2002 IEEE May–June 2002 Every new node of semiconductor technology provides further miniaturization and higher performance, increasing the number of advanced functions that electronic products can offer. Although adding such advanced functions can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very d...

DVCon 2012: 131-II287: Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF

Power management is a critical feature of today’s SoCs, almost as important as functionality. IEEE 1801TM-2009 UPF enables specification of the intended power management infrastructure for an SoC to enable early verification and to drive implementation. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, th...

Infrastructure for Education and Research of SOC/IP in Taiwan

Due to the trend of SOC/IP, design environments of SOC/IP including the system level simulation, hardware software co-simulation, hardware implementation, hardware software co-verification, and rapid prototyping are needed for education and research. The infrastructure provided by Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is use...

Scaling Information Infrastructure: The Case of Next Generation IP in Internet