RF Analog Circuit Design with Scaled CMOS Devices

Because of the prospect of low cost and high integration of scaled CMOS, much effort is being focused on its use for Radio-Frequency (RF) communication circuits. Low Noise Amplifiers (LNA) are essential building blocks for the design of communication systems, and some applications would benefit from the use of low cost CMOS transistor technology to build the LNA. MOS transistors are typically considered to be the noisiest transistor technology, but with the scaling of channel length, MOS transistors have fTs in the tens of gigaHertz (where fT is the transistor unity current gain frequency). High fT results in gain out to higher frequencies, and a lower noise figure at those frequencies. While the noise theory of long channel devices is well understood, and a handful of theories exist for short channel devices, complete noise characterization of short channel devices is in short supply. Our approach is to thoroughly understand the long channel noise theory, examine possible short channel theories, gather measured data on a set of scaled CMOS transistors, and interpret the results. Equipped with this new information, existing LNA designs will be evaluated for use with scaled MOSFETs and design improvements examined.