Design techniques for “soft” single-core embedded processors with predictable behaviour and high levels of performance

This thesis is concerned with the design and implementation of single-processor embedded systems which have strict timing constraints. The focus of the work is on the development of systems which are based on the factors that are involved in making the real-time systems unpredictable. Among various other predictability hampering factors, the problem of shared resource access was the main focus of this research. In previous research this has been demonstrated that the time-triggered co-operative schedulers are more reliable in terms of predictability in real-time applications but there are many applications where some level of pre-emption is inevitable. The inclusion of pre-emption when employed in the systems with shared resources shared resources introduces the possibility of deadlock and data corruption, which can – in turn lead to critical errors or complete system failures. Various methods and protocols have been suggested but these solutions can themselves lead to other issues (such as task “priority inversion”). The target systems comprises on FPGAs on which customised techniques were proposed and implemented to avoid the problems of priority inversion in these systems. In this research adaptation of hardware TRAP and a novel hardware technique TRACE are presented. These techniques were used in a soft-core processor to deal with the shared resources to decrease the jitter and increase the performance of these systems. I dedicate this thesis to my parents, wife and daughters