Testing FPGA Devices Using JBits

Unlike other integrated circuits, SRAM-based FPGA devices present a unique problem for testing. Because of their high level of configurability, it is often difficult to isolate and test device resources. This high level of configurability of FPGA devices, while a drawback for traditional test methods, can also provide unique advantages when performing device test. If configurability is used to tightly control the device functionality, individual components can be isolated and tested. One problem with existing FPGA test approaches is that they typically rely on traditional FPGA design tools to produce their test configurations and then use ASIC-style vectors to detect defects. With the availablity of new design tools which support low-level control and Run-Time Reconfiguration (RTR), detailed, architecture-specific tests can be written in existing high-level languages. This paper discusses the use of Xilinx’s JBits(tm) Toolkit, to provide in-system test using run-time reconfiguration for the Xilinx Virtex(tm) family of devices.