Design of New Low Power –Area Efficient Static Flip-Flops

System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-Flop, which is basic building block, plays a major role in design of complex systems. From the open literature, C2MOS Flip-Flop and PowerPC 603 Flip-Flops are classic structures that dissipate less power. In this paper, two new low power dissipating Flip-Flop architecture are proposed and compared with conventional Flip-Flops. In the proposed Flip-Flop architectures, power dissipation is reduced up to 30% to 40% compared with conventional Flip-Flops and area is also reduced. Johnson counter is designed with the proposed FlipFlops which exhibit low power dissipation. The simulation is done in MENTOR GRAPHICS, Schematic editor, Generic GDK, 130nm technology. Keywords— Power dissipation, Flip-Flop, C2MOS, PowerPC 603, Johnson counter.