Bandwidth-Enhanced Waste-Free Control Technique for Multi-Queue Network Buffers

In high-speed network switches and routers, packet memories have to allow line-speed buffering of data packets. With today’s growing network line-rates, memory bandwidth is an essential constraint to build high-speed network buffers. In this paper, we propose a methodology for designing high-performance network-specific memories using slower lower-cost building blocks. We use parallel memory devices to increase the bandwidth. One possible problem of such architecture is inefficient usage of memory capacities due to division of buffering space between two or more memory pieces. We have concluded that this problem arises from the fact that numbers of accesses to memory blocks are imbalanced due to random nature of packet arrivals and departures. For some specific applications (e.g. network buffers) where accessing the memory is more predictable, this problem could be resolved. What we introduce is a new access control mechanism for a parallel memory system which increases the overall bandwidth while utilizes the entire buffering space. To show a case study, we have designed a double-bandwidth network buffer which uses two half-speed memory devices and supports a multi-FIFO queuing system. The analysis and simulation results show that while the bandwidth of the memory system is increased by a factor of two, the buffering space is totally utilized.