Fault-tolerant architecture for high performance embedded system applications

The architecture of a fault-tolerant embedded computer system is presented. It employs multiple processors for high performance and dual-port memory units for interprocessor communication. The high performance embedded computer (HPEC) system consists of five processors that are partitioned into two sets namely the computing and IO partitions. The computing partition is concerned with computational intensive tasks and it consists of three worker processors. The IO partition performs general-purpose and real-time I/O related tasks. It has two interface processors with high-speed I/O and fast interrupt capabilities. The processor cores for these partitions are selected according to computational and high-speed I/O functions. The HPEC system size can be adjusted for varying needs of computing and real-time I/O without affecting the basic architecture features. The HPEC architecture is fault-tolerant in terms of fault containment and isolation of faulty units. Reliability modeling and analysis of the system indicates that it degrades gracefully under different fault scenarios.