Accelerating Stereoscopic Vision Processing Using Reconfigurable Hardware for Embedded Systems

Real-Time Machine Vision and Image Processing applications have high computational costs, mainly because of the low speed in common hardware/software architectures. In general, embedded systems implemented with microcontrollers and other Von Neumann-based hardware architectures cannot provide the throughput needed by these applications. Since their creation, the FPGAs (Field-Programmable Gate Arrays) have been used to accelerate data intensive computation, such as image processing and computer vision. This work presents an architecture specially developed for processing images in a real-time manner. The architecture allows the pixel stream to go through the processing elements, achieving a high throughput and speed-up performance. Basic filtering such as median, mean and convolution as well as some segmentation algorithms, e.g. erosion, dilation, opening and closing have been implemented in a parallel architecture for each camera of a stereo pair. Three well-known algorithms to extract depth information from stereo images are implemented in parallel, allowing to a comparison among them. The whole system is composed by two CMOS cameras, an low-cost FPGA and a LCD to visualize the processed images.