On Reduction of Substrate Noise in Mixed-signal Circuits

Microelectronics is heading towards larger and larger systems implementedon a single chip. In wireless communication equipment, e.g., cellular phones,handheld computers etc., both analog and digital circuits are required. Ifseveral integrated circuits (ICs) are used in a system, a large amount of thepower is consumed by the communication between the ICs. Furthermore, thecommunication between ICs is slow compared with on-chip communication.Therefore, it is favorable to integrate the whole system on a single chip,which is the objective in the system-on-chip (SoC) approach.In a mixed-signal SoC, analog and digital circuits share the same chip. Whendigital circuits are switching, they produce noise that is spread through thesilicon substrate to other circuits. This noise is known as substrate noise. Theperformance of sensitive analog circuits is degraded by the substrate noise interms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamicrange. Another problem is the design of the clock distribution net, which ischallenging in terms of obtaining low power consumption, sharp clock edges,and low simultaneous switching noise.In this thesis, a noise reduction strategy that focus on reducing the amount ofnoise produced in digital clock buffers, is presented. The strategy is to use aclock with long rise and fall times. It is also used to relax the constraints onthe clock distribution net, which also reduce the design effort. Measurementson a test chip show that the strategy can be implemented in an IC with lowcost in terms of speed and power consumption. Comparisons betweensubstrate coupling in silicon-on-insulator (SOI) and conventional bulktechnology are made using simple models. The objective here is to get anunderstanding of how the substrate coupling differs in SOI from the bulktechnology. The results show that the SOI has less substrate coupling whenno guard band is used, up to a certain frequency that is highly dependent ofthe chip structure. When a guard band is introduced in one of the analyzedtest structures, the bulk resulted in much higher attenuation compared withSOI. An on-chip measurement circuit aiming at measuring simultaneousswitching noise has also been designed in a 0.13 μ SOI process.m