A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis

نویسندگان

  • Aiwu Ruan
  • Shi Kang
  • Yu Wang
  • Xiao Han
  • Zujian Zhu
  • Yongbo Liao
  • Peng Li
چکیده

0026-2714/$ see front matter 2012 Elsevier Ltd. A http://dx.doi.org/10.1016/j.microrel.2012.09.013 Abbreviations: BIST, Built-In Self-Test; CLB, configu under test; D-FF, D flip-flop; EDA, electronic desig programmable gate array; IOB, input/output block; I integrated software environment; JTAG, joint test acti MVP, module verification platform; ORA, output respo component interface express; PIP, programmable-inte transfer level; SM, switch matrix; SPI, software proc testing area; TC, test configuration; TPG, test pattern TV, test vector; XOR, exclusive or; XNOR, exclusiv hardware description language; VHDL, very-high-spee description language; VPI, Verilog hdl procedural inte ⇑ Corresponding author. E-mail address: [email protected] (A. Ruan). This paper presents a BIST system with non-intrusive test pattern generator (TPG) and output response analyzer (ORA) for field-programmable gate array (FPGA) test and diagnosis. The proposed BIST system physically consists of software and hardware parts with two communication channels in between. The TPG and ORA of the BIST circuitry are in the software part while a circuit under test (CUT) is in the hardware part, respectively. One more FPGA is incorporated in the hardware part to act as an interface between the TPG, ORA and the CUT. Algorithms for FPGA test and diagnosis are also presented. Compared with embedded BIST technique, configuration numbers can be reduced without exchanging the TPG, ORA for the CUT when the proposed BIST system is applied to test an FPGA. Also, the proposed BIST system can provide good observability and controllability for the FPGA-under-test due to the proposed algorithms developed for test and diagnosis. No matter what type and array size of an FPGA-under-test is, the CUT can be tested by the proposed BIST system. The BIST system is evaluated by testing several Xilinx series FPGAs, and experimental results are provided. 2012 Elsevier Ltd. All rights reserved.

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عنوان ژورنال:
  • Microelectronics Reliability

دوره 53  شماره 

صفحات  -

تاریخ انتشار 2013