Robust Method for Addressing 12 Gbps Interoperability for High-Loss and Crosstalk-Aggressed Channels

This paper addresses a new methodology for 12 Gbps interoperability that combines a concerted family of pathological channels, internal eye monitoring, and external EQ simulation tools, providing insight into an EQ optimization strategy that addresses the specific channel's mix of crosstalk noise, jitter, and channel loss. This also provides a backplane designer the ability to configure a high-loss, crosstalk aggressed system. The method, combining co-simulation channel optimization, a reconfigurable channel platform, and receiver eye monitoring, has two key benefits; the separation of channel eye opening versus un-equalizable Deterministic Jitter (Dj), and the capability to map loss-crosstalk space for a particular SERDES channel pair, a new concept in SERDES interoperability evaluation. The method is described in detail, followed by relevant case examples using hardware specifically designed for this endeavor. Finally, we compare eye monitor results with the original co-simulation, validating the method. River Technology LLC. James is an experienced design and signal integrity engineer with 30 years experience in complex system design, interconnect, and signal integrity engineering. He has been a consultant to engineering organizations worldwide , with expertise in pre-and post-route signal integrity and timing validation for advanced systems. He earned his B.S. Blankman is a Technical Product Marketing Manager at LeCroy Corporation, focusing on signal integrity products and applications, including the SPARQ series network analyzers and serial data solutions. He has a PhD degree in physics from University of Pennsylvania, and has over 20 years experience developing instrumentation and software solutions for high-energy physicists and electrical engineers. received his BS degree in physics from MIT, and MS and PhD degrees in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices. Eric has written six books on signal integrity and interconnect design and over 200 papers. His latest book " Signal and Power Integrity-Simplified " was published in 2009 by Prentice Hall. He has taught over 6,000 engineers in the last 20 years. Al Neves, Wild River Technology. Al has 30 years of experience in the design and application development of semiconductor products, capital equipment design focused on jitter and signal integrity analysis, and has successfully been involved with numerous business developments and startup activity for the last 13 years. Al focuses on measure-based model development, package characterization, high-speed board design, low jitter design, analysis, and training. He earned a B.S. George Noh, …